The present invention relates generally to electronic devices and, more particularly, to packaged electronic devices and methods of assembling packaged electronic devices.
It is often useful to combine multiple microelectronic devices, such as semiconductor die carrying integrated circuits (ICs), microelectromechanical systems (MEMS), optical devices, passive electronic components, and the like, into a single package that is both compact and structurally robust. Packaging of microelectronic devices has traditionally been carried-out using a so-called two dimensional (2D) or non-stacked approach in which two or more microelectronic devices are positioned and interconnected in a side-by-side or laterally adjacent spatial relationship. More particularly, in the case of ICs formed on semiconductor die (IC die), packaging has commonly entailed the mounting of multiple IC dies to a package substrate and the formation of desired electrical connections through wire bonding or flip-chip (FC) connections. The 2D microelectronic package may then later be incorporated into a larger electronic system by mounting the package substrate to a printed circuit board (PCB) or other component included within the electronic system.
As an alternative to 2D packaging technologies of the type described above, three dimensional (3D) packaging technologies have recently been developed in which microelectronic devices are disposed in a stacked arrangement and vertically interconnected to produce a stacked, 3D microelectronic package. Such 3D packaging techniques yield highly compact microelectronic packages well-suited for usage within mobile phones, digital cameras, digital music players, and other compact electronic devices. Additionally, 3D packaging techniques enhance device performance by reducing interconnection length, and thus signal delay, between the packaged microelectronic devices.
Fan-out Wafer Level Packaging (FOWLP) packaging uses build-up processes for package interconnections. For example, a standard RCP (Redistributed Chip Package) flow attaches a IC die to a wafer-level substrate so that a build-up interconnect layer can be formed at the active side of the IC die to provide external interconnects. In the case of 3D structures where a bond wire is required, e.g., a G-cell device, FOWLP does not easily accommodate formation of other types of interconnect structures, such as wirebond structures.